A D class amplifier of the invention generates a carrier signal Pct based on a master clock Phip without jitter, which is supplied to a PWM circuit. Using a digital PLL including a phase comparator, aloop filter and a carrier oscillator, the generated carrier signal Pct is synchronized with a sampling signal SL. This can produce the carrier signal Pct that is not affected by the jitter containedin the sampling signal SL. Because a phase difference between the sampling signal SL and the carrier signal Pct is fedback to through a feedback circuit, jitter, which can be produced by a slight difference between the sampling signal SL and the master clock Phip can be eliminated.