A separation gate VDMOS device having a low specific on resistance and a method of manufacturing the same are provided, a cellular structure of the device includes: A semiconductor substrate of a first conductivity type, A first layer of semiconductor drift region of a first conductivity type, a second layer of a semiconductor drift region of a a first conductivity type, a semiconductor well region of a second conductivity type, a semiconductor contact region of a first conductivity type, a semiconductor contact region of a second conductivity type, a polysilicon gate electrode, a polysiliconseparation gate electrode, a metal source electrode, a first oxide layer medium, a second oxide layer medium, a third oxide layer medium, a fourth oxide layer medium, and a deep groove. The present invention optimizes the concentration distribution of the drift region to thereby optimize the electric field distribution, As that specific on resistance is reduced under the same withstand voltage condition, when the device operates in the on-off state switching state, due to the reduction of the concentration of the accumulation layer drift region, the MOS capacitor depletion region can be extended wider and the corresponding gate drain capacitance is smaller, so that the dynamic loss of the device is smaller, and the device has a wider safe working region.