The invention invents a method for verifying the interface time sequence of an FPGA (Field Programmable Gate Array) based on a time sequence path. According to the method, static time sequence simulation and functional simulation are verified separately; calculation and analysis are carried out; and an interface time sequence verification result is obtained. With the verification method of the invention adopted, the simulation verification efficiency and time sequence path coverage rate of the interfaces of the FPGA are significantly improved, and the verification effect of the asynchronous interface signals of the FPGA is obvious.