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发明公开
CN107799485A 用于刻划密封结构的方法及设备 审中-实审

用于刻划密封结构的方法及设备
摘要：
本发明涉及用于刻划密封结构的方法及设备。实例性集成电路裸片(图8，801)包含：多个下部层级导体层、位于所述多个下部层级导体层之间的多个下部层级绝缘体层、垂直延伸穿过所述下部层级绝缘体层的多个下部层级导通孔、上覆于所述下部层级导体层上的多个上部层级导体层、位于所述上部层级导体层之间且环绕所述上部层级导体层的多个上部层级绝缘体层、多个上部层级导通孔；至少两个刻划密封(805、807)，其经布置以形成从半导体衬底垂直延伸到在所述集成电路裸片的上表面处的钝化层的垂直阻挡层；及至少一个开口(809)，其垂直延伸穿过所述至少两个刻划密封中的一者且延伸穿过：所述上部层级导体层、所述上部层级导通孔层、所述下部层级导体层及所述下部层级导通孔层。
摘要（英）：

The invention relates to a method and an apparatus for scribe seal structures. An example integrated circuit die includes: a plurality of lower level conductor layers, a plurality of lower level insulator layers between the plurality of lower level conductor layers, a plurality of lower level vias extending vertically through the lower level insulator layers, a plurality of upper level conductor layers overlying the lower level conductor layers, a plurality of upper level insulator layers between and surrounding the upper level conductor layers, a plurality of upper level vias; at least two scribe seals arranged to form a vertical barrier extending vertically from the semiconductor substrate to a passivation layer at an upper surface of the integrated circuit die; and at least one openingextending vertically through one of the at least two scribe seals and extending through: the upper level conductor layers, the upper level via layers, the lower level conductor layers, and the lower level via layers.

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