The invention discloses a method for generating RTL hardware Trojan test vectors. The method mainly includes generation of a control flow chart, concurrent symbol execution, and satisfiability solving and generation of test vectors. The method provided by the invention adopts a method of statically analyzing Veri log codes, and adopts a multi-thread concurrency technology to realize concurrent symbol execution of the Veri log codes, thereby achieving the purpose of rapidly generating test vectors with a high path coverage rate.