The present invention discloses a hardware architecture of f and g operation units in a high-speed, low-power, and area-saving polarized code decoder. The architecture has an addition/ subtraction control signal of the g operation, for indicating the circuit to perform the addition or subtraction operation in the g operation; and an f/g operation control signal, for indicating the circuit to output a result of the f or g operation. The architecture contains an adder, a subtractor, a comparator, a complement unit. According to the architecture disclosed by the present invention, the sum of the two numbers, the difference of the two numbers, and the opposite number of the difference can be calculated in a parallelization manner; according to different combinations of sigh bits and the relative size of the two numbers, the f/g control signal, and the addition/subtraction control signal of the g operation, one piece of candidate data is selected from a plurality of candidate data as a final result; and both the input and the output of the architecture are the binary original code form, so that conversion between multiple different binary representation methods is avoided, the critical path of the hardware architecture of f and g operation units is greatly shortened, the power consumption and area overhead are reduced, and the architecture disclosed by the present invention has wide application prospect in the next generation of mobile communication.