The invention provides a method for preventing electric leakage in the checking process of NOR storage chips. The method comprises the following steps: step one, after erasing is finished, before checking, turning on a small negative-voltage circuit enable signal, and preparing a small negative-voltage passage; step two, in the checking process, in storage units connected onto the same bit line, except checked units, adding a small negative voltage on the bit line of other all storage units, wherein the small negative voltage is determined by the erasing characteristic of the storage units and is lower than a minimum threshold value which can be reached by erased storage units to guarantee that current passes through checked units only in the checking process every time; and step three, adding correction voltage onto the checked unit bit line, wherein the checking result is determined by current on the bit line. According to the method, the generation of leaked current is omitted, and the pertinency for erasing checking is greatly improved, so that the degree of erasing can be controlled more accurately.