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CN106469726B 反熔丝型一次编程的存储单元及其相关的阵列结构 有权

反熔丝型一次编程的存储单元及其相关的阵列结构
摘要：
本发明公开一种反熔丝型一次编程的存储单元结构及其相关的阵列结构。第一掺杂区、第二掺杂区、第三掺杂区与第四掺杂区形成于阱区内。栅极氧化层覆盖于阱区的表面。第一栅极形成于第一掺杂区与第二掺杂区之间的栅极氧化层上，且第一栅极连接至字符线。第二栅极形成于第三掺杂区与第四掺杂区之间的栅极氧化层上，且第二栅极连接至字符线。第三栅极形成于第二掺杂区与第三掺杂区之间的栅极氧化层上，且第三栅极连接至反熔丝控制线。第一掺杂区与第四掺杂区连接至位线。
摘要（英）：

A memory system includes a control block, an antifuse voltage generator, an array voltage generator, and a memory array. The control block is used to output control signals to the memory array according to a memory control data signal. The antifuse voltage generator is used to output an antifuse control signal to the memory array according to a control signal and a driving voltage. The array voltage generator is used to output a selection signal and a following control signal to the memory array according a control signal. The memory array is coupled to the control block, the antifuse voltage generator, and the array voltage generator and configured to access data according to the first control signal, the antifuse control signal, the selection signal, and the following control signal. The first control signal comprises address information of the memory array.

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