The present invention relates to a differential bit line structure of a flash memory and an operation method thereof, wherein the advantages of reliable reading, low program operation voltage, and long service life of storage units are realized. The structure comprises a pair of differential bit lines, and a data buffer circuit. The pair of differential bit lines include a first bit line BL0 and a second bit line BL1, wherein one ends of the first bit line BL0 and the second bit line BL1 are respectively connected to the data buffer circuit. The output end of the data buffer circuit is respectively connected to an output data line DQ and an output reverse data line DQB. The other end of the first bit line BL0 is connected with a first storage unit Cell 0. The other end of the second bit line BL1 is connected with a second storage unit Cell 1. The first storage unit Cell 0 and the second storage unit Cell 1 are different in threshold and collectively represent the information of one bit. When the first storage unit Cell 0 is high in threshold and the second storage unit Cell 1 is low in threshold, data are represented as 0 or 1. Otherwise, data are represented as 1 or 0.