The invention relates to a processor and a method for translating an architecture instruction into a microinstruction. The processor is provided with an execution pipeline for executing the microinstruction and an instruction translator for translating the architecture instruction into the microinstruction. The instruction translator is provided with a memory, a queue and a branch decoder, wherein the memory keeps microcode instructions and provides a plurality of microcode instructions at each clock period; the queue keeps the microcode instructions provided by the memory; the branch decoder decodes the microcode instructions to detect local branch instructions, so that the microcode instructions which are before the local branch instruction in a first program order but do not include the local branch instruction in the first program order in the read microcode instructions are written into the queue, and the local branch instruction in the first program order and the subsequent microcode instructions thereof are written into the queue. The local branch instructions are analyzed by the instruction translator other than the execution pipeline. The microcode translator translates the microcode instructions which are received from the queue at each clock period into the microinstructions to be provided for the execution pipeline.