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发明公开
CN105830204A 功率半导体模块 有权

功率半导体模块
摘要：
本发明缓和功率半导体芯片表面的电场强度，实现制造工序内缺陷的减少、以及可靠性的提高。本发明具有配置在绝缘基板(2)之上的功率半导体芯片(4)，本发明还具有：配线(5)，其与功率半导体芯片的元件区域(4A)处的表面导体图案连接；低介电常数膜(8)，其配置在配线与周边区域(4B)之间；以及封装材料(6)，其是覆盖绝缘基板、功率半导体芯片、配线以及低介电常数膜而形成的，低介电常数膜具有比封装材料低的介电常数。
摘要（英）：

The invention discloses a power semiconductor module. The present invention mitigates field intensity of a power semiconductor chip surface, reduces defects that occur within manufacturing steps, and achieves improvement of reliability. A power semiconductor module is provided with a power semiconductor chip (4) disposed upon an insulating substrate (2), and is additionally provided with a wire (5) connected to a surface conductor pattern on an element region (4A) of the power semiconductor chip, a low dielectric constant film (8) disposed between the wire and a peripheral area (4B), and an encapsulant (6) which is formed so as to cover the insulating substrate, the power semiconductor chip, the wire, and the low dielectric constant film. The low dielectric constant film has a lower dielectric constant than the encapsulant.

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