The invention provides a method and an application for positioning system-on-chip temporal logic errors, and an error rate calculation method. When positioning a system-on-chip temporal logic error, a same test instruction and/or data are/is input into a P-level scan chain, an N-level pipeline and a Q-level scan chain through PAD ports under the same test condition, and test on the test instruction and/or data is achieved through controlling a scan chain enable signal. During the error rate calculation, an error rate of the test instruction and/or data in the environment is obtained according to all processing results. During the reduction of the error rate, a first test instruction and/or data replaces a second test instruction and/or data and achieves the function the same as that of the test instruction and/or data when a processor executes the second test instruction and/or data in the application. The user selects a chip within an error occurrence rate range acceptable by the user according to his application requirement, thereby saving cost and satisfying requirements of the user.