Soft-partitioning of a register file cache is described. Soft-partitioning of a register file cache is implemented by renaming registers associated with an instruction based on which thread, in a multi-threaded out-of-order processor, the instruction belongs to. The register renaming may be performed by a register renaming module and in an embodiment, the register renaming module receives an instruction for register renaming which identifies the thread associated with the instruction and one or more architectural registers. Available physical registers are then allocated to each identified architectural register based on the identified thread. In some examples, the physical registers in the multi-threaded out-of order processor are logically divided into groups and physical registers are allocated based on a thread to group mapping. In further examples, the thread to group mapping is not fixed but may be updated based on the activity level of one or more threads in the multi-threaded out-of-order processor.