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发明公开
CN103957005A 时间数字转换器、全数字锁相环电路及方法 有权

时间数字转换器、全数字锁相环电路及方法
摘要：
本发明公开了一种时间数字转换器，其包括：相位插值电路和时间数字转换电路；相位插值电路用于接收第一参考时钟信号和第二参考时钟信号，并将第一参考时钟信号和第二参考时钟信号进行相位插值，生成第三参考时钟信号，以及将第三参考时钟信号输出给时间数字转换电路；时间数字转换电路用于接收第三参考时钟信号以及第四时钟信号，第三参考时钟信号与第四时钟信号之间的相位差小于第一参考时钟信号与第四时钟信号之间的相位差，以及测量第三参考时钟信号与第四时钟信号的相位差，并将测量到的相位差转换为数字信号输出。本发明提供的时间数字转换器在保证时间精度的同时，能够减少时间数字转换电路中延时单元的使用量。
摘要（英）：

The invention discloses a time-digital converter. The time-digital converter comprises a phase interpolation circuit and a time-digital conversion circuit, wherein the phase interpolation circuit is used for receiving a first reference clock signal and a second reference clock signal, performing phase interpolation on the first reference clock signal and the second reference clock signal to generate a third reference clock signal and outputting the third reference clock signal to the time-digital conversion circuit; the time-digital conversion circuit is used for receiving the third reference clock signal and a fourth clock signal, measuring the phase difference between the third reference clock signal and the fourth clock signal and converting the measured phase difference into a digital signal to be output, wherein the phase difference between the third reference clock signal and the fourth clock signal is smaller than that between the first reference clock signal and the fourth clock signal. According to the time-digital converter, while time accuracy is ensured, the number of delay units in use in the time-digital conversion circuit can be reduced.

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