A network-on-chip-based optimization method for DRAM communication comprises the following steps: step 1 , adopting a multi-port SRAM (Static Random Access Memory) to design a multi-port large cache for each input port, adopting the multi-port SRAM as the data cache of PE to construct a plurality of VCs (Virtual Channel) with configurable numbers and depths; step 2, adopting SPQ (Strict Priority Request) method to set transmission priority, namely setting communication between a node and the DRAM as the highest priority, setting inter-nodes communication as the secondary highest priority, providing service for the highest priority first until finished, then providing service for the secondary highest priority. The network-on-chip-based optimization method increases the utility ratio of a memorizer, reduces delay of the whole system, can effectively improve communication quality with an off-chip DRAM, and does not influence the on-chip inter-nodes communication.