The present invention is a time detection circuit having: a delay unit (30) that starts operation at a first timing relating to the input of a first pulse and that has a plurality of delay units (DU) that delay and output an input signal (Start P); a latch unit (33) that latches the logical state of the plurality of delay units (DU); a count unit (34) that counts on the basis of a clock (CK7) output from any one (DU[7]) of the plurality of delay units; and a latch control unit (32) that enables the latch unit (33) at a second timing relating to the input of a second pulse, and causes the latch unit to execute a latch at a third timing that lags from the second timing by a predetermined time. The latch circuits (D_0 to D_6) that configure the latch unit (33) maintain a disabled state (holding state) until the input of the second pulse (the interval of detected time), and so it is possible to reduce the electric current consumed by the latch unit (33).