The invention discloses a sampling clock control circuit, which comprises a first PMOS (P-channel Metal Oxide Semiconductor) pipe, a second PMOS pipe, a first NMOS (N-channel Metal Oxide Semiconductor) pipe, a time delay module, a reference module, a first inverter and a NAND gate. The drain of the first PMOS pipe is connected with a signal input, the grate is connected with a first clock signal, the source is connected with a signal output, and the substrate is connected with a power supply; the drain of the second PMOS pipe is connected with a second clock signal, the grate is connected with a first internal cable, the source is connected with reference voltage, and the substrate is connected with the power supply; the drain of the first NMOS pipe is connected with the signal input, the grate is connected with the second clock signal, the source is connected with the signal output, and the substrate is connected with ground; the input end of the time delay module is connected with the first clock signal, and the output end is connected with a first time delay clock signal; the input end of the first inverter is connected with the first clock signal, and the output end is connected with a second internal cable; two input ends of the NAND gate are respectively connected with the second internal cable and the first time delay clock signal, and the output ends are respectively connected with the first internal cable; two ends of a capacitor are respectively connected to the first time delay clock signal and the second clock signal; and the reference module is connected to the reference voltage.