The invention relates to the technical field of integrated circuits, and particularly relates to a threshold logic-based 7-3 counter with an SET (single-electron transistors)/MOS (metal-oxide-semiconductor) mixed structure. The 7-3 counter comprises a seven-input threshold logic gate, an eight-input threshold logic gate and a nine-input threshold logic gate; and a circuit only consists of three threshold logic gates and two inverters, and totally consumes five PMOS (P-channel Metal Oxide Semiconductor) tubes, five NMOS (N-channel metal oxide semiconductor) tubes and three SETs (single-electron transistors). A Boolean logic-based CMOS7-3 counter consumes 194 transistors. The average power consumption of the whole circuit is only 6.92 nW. In contrast, as the 7-3 counter provided by the invention is used, the number of the tubes is greatly reduced, the power consumption of the circuit is significantly lowered, and the structure of the circuit is further simplified, therefore, the 7-3 counter is expected to be applied to multipliers, multi-input adders and digital signal processors.