The invention is suitable for the digital communication field, and provides a high-speed parallel interface circuit. The high-speed parallel interface circuit comprises a low voltage differential signaling (LVDS) receiving module, a data sampling module, a data restoring module and a word synchronization module, wherein the LVDS receiving module receives and shapes data; the data sampling module is connected with the LVDS receiving module and samples the data output by the LVDS receiving module under a plurality of phase clocks; the data restoring module is connected with the data sampling module, selects optimal sampling data from oversampling data output from the data sampling module and restores original data by non return to zero inverse (NRZI) decoding; and the word synchronization module is connected with the data restoring module and carries out shift adjustment to the data output by the data restoring module. In the high-speed parallel interface circuit, oversampling and word synchronization are combined to carry out accurate sampling restoration and synchronization to source-synchronous parallel data; and data in the center of an effective window can be dynamically and accurately sampled and restored in real time by dynamically synchronizing, filtering, discriminating phase, selecting the oversampling data and the like.