The invention belongs to the technical field of digital signal processing integrated circuit designs, in particular to a multiplier multiplexing method in a base 2<4> algorithm-based multi-path FFT processor. The invention discloses an improved base 2<4> frequency domain extraction FFT algorithm, which reduces the number of multipliers in FFT processor designs and makes the utilization rate of a constant/multiplex coefficient multiplier for butterfly computation in a single-path FFT processor which is designed on the basis of the method below 50 percent, so as to disclose a multiplexing method for the constant/multiplex coefficient multiplier in a multi-path FFT processor and a corresponding FFT processor structure. The method realizes the multiplexing of the constant/multiplex coefficient multiplier in different paths, reduces the number of the multipliers in the FFT processor, and maintains throughput rate unchanged at the same time.