The invention relates to a logic level converting circuit, which comprises a control end which is connected with an input signal, a first end which is grounded, and a second end which is connected with a second enhancement high-voltage transistor of level output, and also comprises a depletion high-voltage transistor used as a load device, a low-voltage transistor used as an isolating device and a first enhancement high-voltage transistor used as an auxiliary device. In the invention, the (N-Mental-Oxide-Semiconductor) depletion high-voltage transistor is utilized to eliminate the loss of voltage of the logic level without using the high-voltage PMOS (positive channel Metal Oxide Semiconductor) device, and the PMOS low-voltage transistor the grid electrode of which is connected with high level is used as the isolating device to further reduce the grid source voltage of the depletion transistor and increase the threshold value of the depletion transistor, thereby ensuring that no quiescent current is generated when a logic input signal the high level, whereas the NMOS first enhancement high-voltage transistor is used for short-circuit connection with the source leakage end of the low-voltage PMOS device. Analogously, the same effect can also be achieved by changing the NMOS transistor for the PMOS transistor and changing the PMOS transistor for the NMOS transistor.