A data processing apparatus comprising a register bank, a shadow register and an arithmetic operation unit is provided. The register bank comprises a number of registers for respectively storing a number of operands, respectively. The registers comprise a first register, a second register and a third register, and the operands include a first operand, a second operand and a third operand, wherein the registers are n-bit registers, and n is a nature number, the first operand is stored in a first register, the second operand is stored in the second register, and the third operand is stored in the third register. The shadow register is for storing first backup operand for making a backup of a first operand, which is stored in a first register among the registers in response to first control signal. The arithmetic operation unit is for multiplying the third and the second operand and adding a product of the third and the second operand and the first operand to obtain an operational data, and storing the operational data in the first register in response to an arithmetic operation command after the backup of the first operand.