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发明授权
CN101399525B 电压电平箝制电路与比较器模块 失效 - 权利终止

电压电平箝制电路与比较器模块
摘要：
本发明公开一种可设置于一集成电路内部的电压电平箝制电路与高速比较器模块，该集成电路包含有一寄生二极管耦接于一第一电压源与一第二电压源之间。该电压电平箝制电路包含有：一开关模块，耦接于该第一电压源与该第二电压源之间；以及一比较器模块，具有一输出端点耦接于该开关模块、一第一输入端点耦接于该第一电压源以及一第二输入端点耦接于该第二电压源，用于比较该第一电压源的电压电平与该第二电压源的电压电平以产生一输出信号，并将该输出信号传送至该开关模块以控制该开关模块的导通状态来选择性地箝制该第二电压源的电压电平。
摘要（英）：

The invention discloses a voltage level strangulation circuit which can be arranged in an integrated circuit and a high-speed comparator module. The integrated circuit comprises a parasitic diode which is coupled between a first voltage source and a second voltage source. The voltage level strangulation circuit comprises a switch module and a comparator module; wherein, the switch module is coupled in the first voltage source and the second voltage source; the comparator module is provided with an output endpoint which is coupled in the switch module, a first input endpoint which is coupled in the first voltage source and a second input endpoint which is coupled in the second voltage source, and is used for comparing the voltage level of the first voltage source and the voltage level of the second voltage source so as to generate an output signal and conveys the output signal to the switch module so as to control the conducting state of the switch module for selectively clamping the voltage level of the second voltage source.

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