The invention relates to a method for measuring the time delay of a receiving machine. The receiving machine comprises an FPGA (Field Programmable Gate Array), a digital signal processor and a built-in clock pulse source. The FPGA is used to synchronize baseband digital signals and demodulating and outputting I and Q data, and the digital signal processor is used to conduct signal processing of the I and Q data, while the clock pulse source provides clock pulse to the FPGA and the outer clock port of the receiving machine. The invention has the advantages of measuring the time delay of a receiving machine without increasing a spare interface and modifying FPGA programs especially since the inner clock pulse of the receiving machine triggers the measuring signals of the outer measuring signal source.