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发明授权
CN101001085B 信号采样保持电路 有权

信号采样保持电路
摘要：
本发明公开了一种信号采样保持电路，包括第一PMOS管、第二PMOS管、第三PMOS管、第四PMOS管、采样电容Cs及控制器，第一PMOS管与第三PMOS管连接形成第一节点，第二PMOS管与第四PMOS管连接形成第二节点，第一节点和第二节点之间连接有采样电容，第一PMOS管和第三PMOS管衬底浮置，在采样阶段，第一PMOS管和第三PMOS管导通，并在输入信号中进行采样，将信号采样到采样电容Cs；在转移阶段，控制器控制第二PMOS管和第四PMOS管导通，对采样电容的电荷进行输出。本发明的信号采样保持电路，使PMOS管的衬底浮置，保证PMOS管不会因栅压过大被击穿，并有效采集负信号。
摘要（英）：

This invention discloses a holding circuit for sampling signals including PMOS tubes M1, M2, M3 and M4, sample capacitor Cs and a controller, in which, M1 and M2 are connected to form a first node N1,M3 and M4 are connected to form a second node N2, and a sample capacitor is set between n1 and n2, the substrates of M1 and M2 are floated, M1 and M3 are conducted in the sample period to sample in the input signals and send the signal to the sample capacitor Cs, in the holding period, said controller controls the conduction of M2 and M4 to output charges of the capacitor.

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