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发明授权
CN100578934C 含异步仲裁器单元的延迟线校准电路 失效 - 权利终止

含异步仲裁器单元的延迟线校准电路
摘要：
本发明涉及延迟线校准电路。校准电路(10)包括具有用于确定两个信号中哪一个先到达的装置的仲裁器电路(14)；各包括用于接收时钟信号的输入端的第一和第二同步单元(12、13)，并且它们中的一个具有用于在一个时钟周期之后输出时钟信号的装置；以及包括连接到仲裁器电路(14)的输出端的输入端的校准电路(15)，用于从其接收信号，该信号用于指示从延迟线(11)输入到仲裁器电路(14)的信号是超前还是滞后于从第二单元(13)输入到仲裁器电路(14)的信号，校准电路(15)还被连接到延迟线(11)，用于根据从仲裁器电路(14)接收到的信号校准延迟线。本发明提供了延迟线的改进校准。
摘要（英）：

A delay line calibration circuit is disclosed herein. The calibration circuit has an arbiter circuit having a unit for determining which of two signals that arrive first; a first and a second synchronous element each having an input for receiving a clock signal, and one of them having a unit for outputting the clock signal a clock period later; and a calibration circuit having inputs connected to the outputs of the arbiter circuit for receiving a signal from it indicative of whether the signal input to the arbiter circuit from the delay line is ahead or after the signal input to the arbiter circuit from the second element, the calibration circuit further being connected to the delay line for calibrating the delay line in accordance with the signal received from the arbiter circuit. The invention in at least one embodiment provides improved calibration of delay lines.

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